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Design rules in Semiconductor Foundry is a text designed to serve as a comprehensive and up-to-date manual for process, device, layout, and design engineers. Written for the professionals, the book belongs on the bookshelf of microelectronic discipline experts. Over 50% of the integrated circuits are manufactured nowadays at wafer foundries. The aim of this book is to present a foundry integrated perspective of these fields. The book includes several chapters, which were carefully selected to cover the main topics process, device, layout, and design engineers are dealing in their work.
This is the first available book dedicated exclusively to describing the layout and reliability design rules. It should provide the semiconductor engineers, researchers and microelectronic students comprehensive knowledge about the design layout and the correlation with the manufacturing processes, as well as the electrical and reliability performances. The book was designed to serve as a comprehensive and up-to-date manual for process, device, layout, and design engineers. The rich list of examples, together with the easy-to-read DR tables and related figures, make this book a good technical book for both students that now gets into the field, and for experienced engineers that seek for a good source of information.
Preface
Acknowledgment
Contributors
Layout Design Rules: Definition, Setting, and Scaling
Front-End-of-Line Topological Design Rules
Back-End-of-Line Topological Design Rules
Coverage Rules and Insertion Utilities
Design Rules, Guidelines, and Modeling for Analog Modules
Stress-Related Layout Design Rules and Modeling
Dedicated Design Rules for Memory Modules
Planar CMOS Process Flow for Digital, Mixed-Signal, and RFCMOS Applications
Reliability Driven Design Rules
Index