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CMOS operational amplifiers are discussed. Both single- and two-stage architectures are treated. Opamps with constant-gill input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The work presented here is a result of Ph.D dissertation research conducted by Satoshi Sakurai at the Ohio State University, with Professor Mohammed Ismail as his adviser. The project was initiated in the Spring of 1992, after the first set of CMOS constant-gill input stages were introduced by a group from Technische Universiteit Delft and Universiteit Twente, The Netherlands. These earlier versions of circuits are discussed in this book along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits were completed in June, 1994. Readers are presumed to have some understanding of basic analog integrated circuit design concepts in order to fully appreciate the work presented.
However, the topics are presented in a logical order and the circuits are explained in great detail, such that the book can be read and enjoyed by those without much experience in analog circuit design. In the first part of the book, motivations behind the work are stated. The necessity for the reduction in the power supply voltage is discussed in Chapter I, and the advantages of having rail-to-rail input stage with constant-gill characteristics are pointed out. In Chapters III, IV, and V, constant-gm input stages are presented and their operations are explained. The new input stages introduced in Chapter V are used in the design of various opamps. The design of these opamps and their computer simulation results are given in Chapters VI, VIT, and VIII.
Performances of opamps fabricated using MOSIS service are presented in Chapter IX where the effectiveness and the usefulness of the constant-gill input stages are clearly demonstrated. Measurement techniques used, e.g. for measuring the transconductance, the gainbandwidth, the phase margin etc., are described together with process parameters used and SPICE netlists of all circuits