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In many ways, it is correct to view engineering as an inexact science. Yes, as with mathematics and the hard sciences, there is often a need for proofs and exacting arguments. However, there is often, also, the need to produce, in a timely manner, just enough. That is to say, there are circumstances when a “sufficient” solution today is better than a “perfect” solution tomorrow. This mind-set is often the case for integrated circuit design, in general, and for stdcell IP design, in particular. As just one example, a classical way of implementing a flip-flop that has the added functionality of both an “asynchronous set” and an “asynchronous reset” is to add just enough circuitry to the flip-flop for each of those two additional functions to operate independently. Doing so assures a minimal sized stdcell in both net-list size and in layout area. However, it means that the flip-flop operates un-tractably when the controls for those two asynchronous functions are operated together. This especially causes issues if the control signals are deasserted simultaneously. Dependent on the race between the two control signals, operating in a real world parasitic environment, such a flip-flop might settle either into a “set” configuration, or into a “reset” configuration, or into a nonsensical combination of those
two states, or even settle into some meta-stable oscillation mode. The “perfect” solution would be to define a flip-flop circuit that assures some a priori tractable resolution in such an event. That means added transistors to the flip-flop design, further meaning that the flip-flop is larger, probably slower, and definitely more power hungry. In addition, while the addition of such circuitry can certainly reduce the chances of the cell going into some improper operation upon the simultaneous removal of both asynchronous signals, it cannot totally eliminate the chance of this occurring. Therefore, since the “perfect design” produces a larger, slower, more power hungry device and one that is doomed to failure anyway, the “sufficient design” is just to use the minimal circuit additions and to note, in a release document, that the flip-flop operation is not guaranteed under such
conditions. This assures a smaller, faster design and allows the user of the flip-flop to develop proper control over the signals that operate the two asynchronous functions (or to ignore the warning at the user’s own risk). In other words, the stdcell library designer should trust that the integrated-circuit designer is competent to do his/her job. While it might be the concerted wish of the integrated-circuit design community that
the typical stdcell library (or other IP) offerings that they might be required to use in their design work is of the “perfect” mode, it is far more likely, and even desirable, for those offerings to be of the “sufficient” mode. The knowledge of the existence of the inexactitudes in those “sufficient” mode libraries, the ability to spot where in those libraries such inexactitudes might be, and the ability to take advantage of those inexactitudes in order to produce smaller, faster, cheaper designs, is the underlying cause for the writing of this book. This book is based on personal experience gained while producing stdcell libraries, for multiple companies, both on the integrated-circuit design side and on the IP development side, for technology nodes ranging from 1.25um in the early 1980s to 14nm today