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The Verilog-A language is derived from Verilog HDL for the description of high-level analog behaviors. Used in conjunction with a Spice simulator, The Verilog-A language expands the simulation capabilities for analog and mixed-signal systems to topdown and bottom-up methodologies. The proposed Verilog-A language is described in the Language Reference Manual (LRM) draft prepared by a standards working group of the Open Verilog International (OVI) organization. The LRM Version 1.0, August 1, 1996 is not yet fully defined and is subject to change. As such, the material in this book focuses on the core aspects of the Verilog-A language as presented in the LRM and the work within the OVI Verilog-A Technical Subcommittee. The goal of this book is to provide the designer a brief introduction into the methodologies and uses of analog behavioral modeling with the Verilog-A language. In doing so, an overview of Verilog-A language constructs as well as applications using the language are presented. In addition, the book is accompanied by the Verilog-A Explorer IDE (Integrated Development Environment), a limited capability Verilog-A enhanced Spice simulator for further learning and experimentation with the Verilog-A language. This book assumes a basic level of understanding of the usage of Spicebased analog simulation and the Verilog HDL language, although any programming language background and a little determination should suffice