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Continuing from volume 1, this volume outlines circuit- and system-level design approaches and issues for these devices.
Topics covered include self-healing analog/RF circuits on-chip gate delay variability measurement in scaled technology FinFET SRAM circuits nanoscale FinFET devices for PVT aware SRAM low leakage variability aware CMOS logic circuits thermal effects in MWCNT VLSI interconnects an accurate PVT-aware statistical logic library for nano-CMOS integrated circuits SPICEless RTL design optimization of nano-electronic digital integrated circuits power-delay trade-off driven optimal scheduling of CDFGs during high level synthesis green on-chip inductors for three-dimensional integrated circuits 3D NoC -- a promising alternative for tomorrow’s nano-system design and DNA computing
Preface
Self-healing analog/RF circuits
On-chip gate delay variability measurement in scaled technology node
Nanoscale FinFET devices for PVT-aware SRAM
Data stability and write ability enhancement techniques for FinFET SRAM circuits
Low-leakage techniques for nanoscale CMOS circuits
Thermal effects in carbon nanotube VLSI interconnects
Lumped electro-thermal modeling and analysis of carbon nanotube interconnects
High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era