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VLSI CAD has greatly benefited from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satisfiability (SAT), e.g. in logic synthesis, verification or design-for-testability. In recent practical applications, BDDs are optimized with respect to new objective functions for design space exploration. The latest trends show a growing number of proposals to fuse the concepts of BDD and SAT.
This book gives a modern presentation of the established as well as of recent concepts. Latest results in BDD optimization are given, covering different aspects of paths in BDDs and the use of efficient lower bounds during optimization. The presented algorithms include Branch and Bound and the generic A∗-algorithm as efficient techniques to explore large search spaces.
The A∗-algorithm originates from Artificial Intelligence (AI), and the EDA community has been unaware of this concept for a long time. Recently, the A∗-algorithm has been introduced as a new paradigm to explore design spaces in VLSI CAD. Besides AI search techniques, the book also discusses the relation to another field of activity bordered to VLSI CAD and BDD optimization: the clausal representation as a SAT problem.
When regarding BDD optimization, mainly the minimization of diagram size was considered. The present book is the first to give a unified framework for the problem of BDD optimization and it presents the respective recent approaches. Moreover, the relation between BDD and SAT is studied in response to the questions that have emerged from the latest developments. This includes an analysis from a theoretical point of view as well as practical examples in formal equivalence checking. This book closes the gap between theory and practice by transferring the latest theoretical insights into practical applications.
In this, a solid, thorough analysis of the theory is presented, which is completed by experimental studies. The basic concepts of new optimization goals and the relation between the two paradigms BDD and SAT have been known and understood for a short time, and they will have wide impact on further developments in the field.
Preliminaries
Exact Node Minimization
Heuristic Node Minimization
Path Minimization
Relation between SAT and BDDs
Final Remarks
Within the last 10-13 years Binary Decision Diagrams (BDDs) have become the state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean functions. Today, BDDs are widely used and in the meantime have also been integrated in commercial tools, especially in the area of verification and synthesis.
The interest in BDDs results from the fact that the data structure is generally accepted as providing a good compromise between conciseness of representation and efficiency of manipulation. With increasing number of applications, also in non CAD areas, classical methods to handle BDDs are being improved and new questions and problems evolve and have to be solved.
The book should help the reader who is not familiar with BDDs (or DDs in general) to get a quick start. On the other hand it will discuss several new aspects of BDDs, e.g. with respect to minimization and implementation of a package. This will help people working with BDDs (in industry or academia) to keep informed about recent developments in this area.
Notations and Definitions
Decision Diagrams
Theoretical Aspects
Minimization of Decision Diagrams: Classical Methods
Minimization Using Symmetries
Alternative Minimization Concepts
Implementational Concepts
A Case Study: Two-Level AND/EXOR Minimization
Conclusions