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The reconfigurable cryptographic processor is one of the ideal hardware implementations for encryption and decryption algorithms. Compared with traditional cryptographic processors, the reconfigurable cryptographic processor can meet the requirements of cryptographic application for high security, high energy efficiency, and high flexibility. In terms of security, the function of the dynamically reconfigurable computing architecture is not determined by either the hardware or the software alone, but it is dynamically defined by both the software programming and the hardware programming. The reconfigurable computing architecture has the “blank chip” feature after the power supply is cut off. Therefore, it is difficult to obtain the cryptographic algorithms through invasive attacks. Meanwhile, the execution model of the dynamically reconfigurable computing architecture has specialization and is indeterministic and it is very difficult to conduct side-channel attacks on it such as power analysis attacks, fault attacks, and electromagnetic attacks through behavioral modeling. Therefore, the dynamically reconfigurable computing architecture has high security against physical attacks. In terms of performance and power consumption, the dynamically reconfigurable computing architecture performs operations mainly by using a spatially parallel method, which is very suitable for the feature of cryptographic algorithms, and its energy efficiency (i.e., performance per watt) is high. In terms of functional flexibility, the reconfigurable computing architecture can change its hardware functions at runtime to fit them for different cryptographic algorithms and execution modes, and it has excellent flexibility. With the constant development of physical attack means in recent years, even if the security of cryptographic algorithms is very good, the attacker can still steal key information by using invasive or noninvasive physical attacks on the bottom-level cryptographic processor. Because the reconfigurable cryptographic processor has the above-mentioned outstanding advantages in resisting physical attacks, it has gradually become a hot research direction of cryptographic chips and a lot of relevant achievements on it have been published at the top conferences of the cryptographic field and in periodicals of the cryptographic field in recent years.
Traditional cryptographic processors are mainly the application-specific integrated circuits (ASICs) and the instruction set architecture processors (ISAPs). The ASIC has obvious disadvantages in security and flexibility. By reversely analyzing ASIC chips, attackers can crack the cryptographic algorithms by the circuit implementation and steal the secret information being processed. In addition, the ASIC chip can only implement the specific cryptographic algorithms and it almost has no functional flexibility. Therefore, it cannot meet the rapidly developing demands of applications. The ISAP also has some security problems. Because it is easy to model the execution process of the system, the ISAP is likely to suffer noninvasive side-channel attacks. Meanwhile, the energy efficiency of the ISAP has been unable to meet the demands of current practical applications. The reconfigurable cryptographic processor has solved these difficult problems very well, and it has gradually been applied in practice. Therefore, it is likely that the reconfigurable cryptographic processor will be both the research and application directions of the future cryptographic processor