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The fast trend towards digital processing of analogue signals in an increased number of application fields has stimulated significant research efforts in the area of data converters implemented in CMOS technologies. High-speed high-resolution Analogue-to-Digital Converters (ADCs) are required in the front-end receive paths of many modern communication systems. For input signal bandwidths larger than a few MHz, self-calibrated pipelined solutions show speed and power advantages when compared to other architectures. The work reported in this Book comprises two major research areas in the field of high-speed self-calibrated pipelined ADCs. The first area covers the study and the successful implementation of a novel analogue selfcalibration technique required to extend the limited linearity of front-end stages in pipelined Analogue-to-Digital (A/D) converters, since component fabrication accuracy is limited and rarely stable or well characterised during the useful life of any process. The second area comprises the development of a systematic design methodology for the optimisation of high-speed selfcalibrated pipelined A/D converters that takes into account physical limitations for practical integrated circuit implementations, including thermal noise and component matching accuracy. It is demonstrated that multi-bit, rather than single-bit resolution-per-stage architectures have to be considered for optimising the resulting silicon area and power dissipation. Several practical realisations with consistent measured results clearly assess the feasibility of the proposed self-calibration technique, validate the main theoretical findings and demonstrate the attractiveness in terms of power dissipation and reduced die area of the established design methodology