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The evolution of the CMOS technology brings many challenges to analog designers. The scaling-down of the transistor feature size has a big impact on analog circuit design, because it considerably degrades the performance of an analog circuit. As an interface between the analog circuit and the digital circuit, the ADC is moving into nanometer CMOS technologies due to the advantages for the digital circuit. Consequently, the reduced supply voltage and the degraded device characteristic are inevitable problems in ADC design. Many efforts have been devoted to cope with these problems to make an ADC design in nanometer CMOS technologies. In this text, the circuit level approach and the system level approach are presented for low-power lowvoltage S--D ADC design in nanometer CMOS technologies. At the circuit level, specially designed circuit building blocks suitable for nanometer CMOS technologies are introduced. At the same time, low-power consumption is also addressed. Following a low-power low-voltage operational amplifier design, a lowpower low-voltage S-D modulator design is presented in a 90-nm CMOS technology. The total power consumption is 140 μW under a 1.0-V power supply voltage. The modulator reaches a peak SNR of 85 dB and a dynamic range of 88 dB in a 20-kHz signal bandwidth. This design is the first S-D modulator design in a 90-nm CMOS technology and reaches a very high figure-of-merit. This design demonstrates the feasibility of designing high-performance S-D ADCs in nanometer CMOS technologies. At the system level, a full-feedforward S-D topology suitable for the S-D ADC design in nanometer CMOS technologies is introduced. The most important feature of this topology is that the signal transfer function is unity, which is fairly independent of the building block characteristics. With careful signal scaling, signal swings inside the loop filter can be largely suppressed, which is highly desirable for low-voltage designs. A detailed analysis is presented in this text, leading to optimized loop coefficients. Behavioral simulations reveal that requirements for building blocks are quite relaxed in this topology. Implemented in a 130-nm CMOS technology, the proposed fourthorder full-feedforward S-D modulator reaches a 88-dB DR with a power dissipation of 7.4 mW in a 500-kHz signal bandwidth under a 1.0-V power supply voltage. This design is the first design using the full feedforward S-D topology and reaches the highest conversion speed among all the 1-V S-D modulators to date. This design proves that the proposed full-feedforward S-D topology is an excellent topology for low-power low-voltage S-D ADC designs in nanometer CMOS technologies