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This book is designed to act as a practical design guide for CMOS PLL’s designers. Phase-locked loops are circuits commonly found in communication
front ends, and are especially relevant in OFDM-based systems. Within in its composition there is a wide variety of circuits ranging from digital to RF analog to make this a unique building block. Its diversity allows the student to become familiar with a variety of design techniques and for professionals it remains a challenging task. We have no desire to duplicate current available information in existing publications. We believe our book documents in clear sequential order practical information from published works. Our sources have included published scientific papers and international conference presentations. This coupled with our own experience as designers and lecturers give the reader a complete detailed account of the pros and cons experienced using the different approach methods. Our goal is to simply bridge what we believe to be, the gap between CMOS technology and PLL theory books. Chapters 1 to 5 present the different alternatives available for RFIC designers in order to tackle the PLL implementation with CMOS technologies. The structure of these chapters follows the building block architecture of PLL. For each block, the principle of operation is presented, introducing the CMOS realizations available in bibliography with references and discussion of previous works. We have included the phase noise analysis at this juncture of the book as it is one of the most important parameters in the design process. In Chapter 5 we present layout considerations with photographs of our own designs marking the key points of the design. Chapters 6 to 11 outlines the design case and the characterization setup. These chapters are geared to students and novel designers. Its objective being the illustration of the procedures used to develop a complete PLL, using the methodology, building blocks and models previously presented. We set out to write a book that would enhance existing available works and act as a valuable learning tool for designers. In a technological climate of change, we as engineers must consistently be innovative in our approach and avail of all opportunities for learning new applications for existing technologies. In bridging the gap between CMOS technology and PLL theory books, we believe the sequence of information and layout of this publication makes it a valuable additional learning tool. In conclusion, we hope you find the book educational, challenging and helpful